An FPGA Resource Adaptable General Neural Network Accelerator

Abstract

As Artificial Intelligence is becoming embedded in people’s lives, the evolution of Internet of Things is moving towards edge computing where the speed and power consumption in data processing is critical. The feature of re-programmability and power efficiency has made FPGA a promising edge processing hardware platform for accelerating deep neural networks. An FPGA ‘resource-adaptable’ neural network accelerator is proposed in this paper. The architecture and behavior of this accelerator is determined only by the way its C program is designed. The design of the architecture, programmed in C code, is converted to a description in the form of a hardware description language such as VHDL or Verilog. The conversion is carried out by High-Level Synthesis (HLS) software provided by the Xilinx Vivado development package. Since the accelerator architecture is fully parameterized in the C code, it can be tailored freely according to the availability of FPGA logic elements, and hence implemented by different types of FPGA. The proposed accelerator has a configurable register unit, which enables it to dynamically adjust the computing behavior according to the computing requirements of different neural networks without changing the design of architecture.