Evaluating the Hardware Performance Counters of an Xtensa Virtual Prototype

Omotosho, Adebayo orcid iconORCID: 0000-0002-1642-7610, IIahi, Sirine, Villegas Castillo, Ernesto Cristopher, Hammer, Christian and Sauer, Christian (2023) Evaluating the Hardware Performance Counters of an Xtensa Virtual Prototype. In: 2023 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), 3-5 May 2023, Tallinn, Estonia.

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Official URL: https://doi.org/10.1109/DDECS57882.2023.10138942


Embedded systems’ hardware and software stacks are becoming more complex requiring more development time, time to market, and cost, which contributes to delayed delivery of these silicon devices. A virtual prototype (VP) provides an embedded systems architecture simulator for application development and testing purposes. In this paper, we developed and present the first virtual prototype of the Xtensa LX7 microprocessor that evaluates the performance of its emulated hardware performance counters (HPCs) with those collected from an actual Xtensa LX7 hardware. Seven machine learning models were developed and trained to find the relationships between the two different datasets for the sample application of classifying return-oriented programming (ROP) attacks. Our experiments show that the obtained micro-architectural characteristics on the VP are on average about 70% similar and thus permit early simulation capabilities for developers and testers.

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